1. Field of the Invention
The present invention relates to a liquid crystal display (LCD), and more particularly, to a demultiplexer for an LCD and a driving method thereof.
2. Discussion of the Related Art
In general, an LCD controls light transmittance of liquid crystals in accordance with a video signal so that a picture corresponding to the video signal can be displayed on the LCD. The LCD includes an LCD panel having liquid crystal cells arranged in an active matrix type, and driving circuits for driving the LCD panel. In the LCD panel, a plurality of data lines and a plurality of gate lines are intersected, and pixel driving thin film transistors (TFTs) are provided at respective intersected portions. The driving circuits of the LCD include a data driving circuit for supplying a data to the data lines of the LCD panel, and a gate driving circuit for supplying a scanning pulse to the LCD panel. Further, the driving circuits may include a demultiplexer provided between the data driving circuit and the data lines to distribute outputs of the data driving circuit into the data lines. The demultiplexer reduces the number of the outputs of the data driving circuit to simplify the data driving circuit and reduce the number of data input terminals of the LCD panel.
FIG. 1 shows a related art active matrix LCD. As shown in FIG. 1, the related art active matrix LCD includes an LCD panel 13 having m data lines DL1-DLm and n gate lines GL1-GLn crossing each other and a pixel driving TFT 16 provided at each intersection, a demultiplexer 14 provided between a data driving circuit 11 and the data lines DL1-DLm, and a gate driving circuit 12 for sequentially supplying a scanning pulse to the gate lines GL1-GLn.
The pixel driving TFT 16 applies a data signal from each of the data lines DL1-DLm to a pixel electrode 15 of a liquid crystal cell in response to a scanning signal from each of the gate lines GL1-GLn. Herein, the pixel driving TFT 16 has a gate electrode connected to a corresponding one of the gate lines GL1-GLn, a source electrode connected to a corresponding one of the data lines DL1-DLm, and a drain electrode connected to the pixel electrode 15 of the liquid crystal cell.
The data driving circuit 11 converts digital video data into analog gamma voltages, and makes a data time division for one line to apply the voltages to m/3 source lines SL1-SLm/3. The mn/3 demultiplexers 14 are arranged parallel to each other between the data driving circuit 11 and the data lines DL1-DLm. Each of the demultiplexers 14 includes first through third TFTs (hereinafter referred to as “MUX TFT”) MT1, MT2 and MT3. The first through third MUX TFTs MT1, MT2 and MT3 make a time division of data input over one signal line in response to different control signals Φ1, Φ2 and Φ3 to apply these control signals to three data lines. The gate driving circuit 12 sequentially applies scanning pulses to the gate lines GL1-GLn by using a shift register and a level shifter.
FIG. 2 shows control signals Φ1, Φ2 and Φ3 and scanning pulses SP of the demultiplexer 14. As shown in FIG. 2, the scanning pulse SP has a gate high voltage Vgh during approximately one horizontal period 1H while maintaining a gate low voltage Vgl during the remaining period. A duty ratio of the scanning pulse SP is approximately one by several hundreds because one frame interval includes hundreds of horizontal periods.
Each of the control signals Φ1, Φ2 and Φ3 has the gate high voltage Vgh during approximately ⅓ horizontal period every horizontal period. A duty ratio of each of the control signal Φ1, Φ2 and Φ3 is about ½ to 1 by several numbers because each control signal is generated every horizontal period. Herein, when a duty ratio of each control signal is ½, only two of the MUX TFTs are included in a single demultiplexer.
The MUX TFTs MT1, MT2 and MT3 and the pixel driving TFT 16 are directly and simultaneously provided on a glass substrate of the LCD panel 13, and have the same swing width between the gate high voltage Vgh and the gate low voltage Vgl. If the MUX TFTs MT1, MT2 and MT3 are supplied with gate voltages having the same polarity for a long time, that is, if they receive a positive gate bias stress or a negative gate bias stress, variation and deterioration of operation characteristics occur more easily. The variation and deterioration results from the MUX TFTs MT1, MT2 and MT3 having a longer gate voltage application time than the pixel driving TFT 16 as shown in FIG. 2. Particularly, if the MUX TFTs MT1, MT2 and MT3 are formed from amorphous silicon TFT, then the variation and deterioration of operation characteristics occur more easily against the positive gate bias stress or the negative gate bias stress because a semiconductor layer structure of the amorphous silicon TFT has more defects than those of polycrystalline silicon TFT (poly-Si TFT). The variation in operation characteristics of the MUX TFTs MT1, MT2 and MT3 can be seen from experimental results in FIGS. 3 and 4.
FIGS. 3 and 4 show experimental results indicating that a characteristic change of a sample hydride amorphous silicon (a-Si:H TFT) happened when a positive gate bias stress and a negative gate bias stress were applied to the sample a-Si:H TFT having a channel width/channel length W/L of 120 μm/6 μm, respectively. In FIGS. 3 and 4, the horizontal axis represents a gate voltage [V] of the sample a-Si:H TFT while the vertical axis represents a current [A] between the source terminal and the drain terminal of the sample a-Si:H TFT.
FIG. 3 shows a threshold voltage and a movement in a transfer characteristic curve of a TFT according to a voltage application time when a voltage of +30V is applied to a gate terminal of the sample a-Si:H TFT. In FIG. 3, as the time when a high positive voltage is applied to the gate terminal of the a-Si:H TFT becomes longer, the transfer characteristic curve of the TFT is moved more to the right side 31 and the threshold voltage of the a-Si:H TFT rises.
FIG. 4 shows a threshold voltage and a movement in a transfer characteristic curve of a TFT according to a voltage application time when a voltage of −30V is applied to the gate terminal of the sample a-Si:H TFT. In FIG. 4, as the time when a high negative voltage is applied to the gate terminal of the a-Si:H TFT becomes longer, the transfer characteristic curve of the TFT is moved more to the left side (41) and the threshold voltage of the a-Si:H TFT is lowered.
FIG. 5 shows an accumulation of gate voltage stresses undergone at each of the MUX TFTs MT1, MT2 and MT3. In FIG. 5, as the gate voltage stresses of the MUX TFTs MT1, MT2 and MT3 are accumulated whenever the same polarity of the control signals Φ1, Φ2 and Φ3 are applied thereto, a threshold voltage of each of the MUX TFTs MT1, MT2 and MT3 gradually rises or falls. As the threshold voltage of the MUX TFT rises or falls in this manner, an operation of the demultiplexer 14 becomes unstable, thereby causing difficulty to normally drive the LCD.